edi88512ca 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. 512kx8 monolithic sram, smd 5962-95600 features access times of 15, 17, 20, 25, 35, 45, 55ns data retention function (lpa version) ttl compatible inputs and outputs fully static, no clocks organized as 512kx8 commercial, industrial and military temperature rang es 32 lead jedec approved evolutionary pinout ? ceramic sidebrazed 600 mil dip (package 9) ? ceramic sidebrazed 400 mil dip (package 326) ? ceramic 32 pin flatpack (package 344) ? ceramic thin flatpack (package 321) ? ceramic soj (package 140) 36 lead jedec approved revolutionary pinout ? ceramic flatpack (package 316) ? ceramic soj (package 327) ? ceramic lcc (package 502) single +5v (10%) supply operation the edi88512ca is a 4 megabit monolithic cmos stat ic ram. the 32 pin dip pinout adheres to the jedec evo lu tion ary stan dard for the four megabit device. all 32 pin packages are pin for pin up grades for the single chip enable 128k x 8, the edi88128cs. pins 1 and 30 be come the higher order addresses. the 36 pin revolutionary pinout also adheres to the jedec stan dard for the four megabit device. the cen ter pin power and ground pins help to reduce noise in high performance systems. the 36 pin pinout also allows the user an upgrade path to the future 2mx8. a low power version with data retention (edi88512lpa) is also available for battery backed applications. military product is available compliant to appendix a of mil- prf-38535. *this product is subject to change without notice. 36 pin top view pin description i/o 0-7 data inputs/outputs a0 -18 address inputs we# write enables cs# chip selects oe# output enable v cc power (+5v 10%) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a 0-18 i/o 0-7 we# cs# oe# fig. 1 pin configuration 32 pin top view nc a18 a17 a16 a15 oe# i/o7 i/o6 vss vcc i/o5 i/o4 a14 a13 a12 a11 a10 nc 36 pin revolutionary a0 a1 a2 a3 a4 cs# i/o0 i/o1 vcc vss i/o2 i/o3 we# a5 a6 a7 a8 a9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 32 pin evolutionary a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 a17 we# a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3
edi88512ca 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. absolute maximum ratings parameter value unit voltage on any pin relative to vss -0.5 t a 7.0 v operating temperature t a (ambient) commercial 0 t a +70 c industrial -40 t a +85 c military -55 t a +125 c storage temperature, plastic -65 t a +150 c power dissipation 1.5 w output current 20 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 3.0 v input low voltage v il -0.3 +0.8 v parameter symbol condition max unit address lines c i v in = vcc or vss, f = 1.0mhz 12 pf data lines c o v out = vcc or vss, f = 1.0mhz 14 pf these parameters are sampled, not 100% tested. capacitance (t a = +25c) truth table oe# cs# we# mode output power x h x standby high z icc 2 , icc 3 h l h output deselect high z icc1 l l h read data out icc1 x l l write data in icc1 note: stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and func tion al operation of the device at these or any other conditions greater than those in di cat ed in the operational sections of this spec i ? ca tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 ? vcc q figure 1 figure 2 255 ? 5pf 480 ? ? ac test conditions dc characteristics (v cc = 5v, t a = -55c to +125c) parameter symbol conditions min max units input leakage current i li v in = 0v to v cc -10 10 a output leakage current i lo v i / o = 0v to v cc -10 10 a operating power supply current i cc 1 we#, cs# = v il , i i / o = 0ma, min cycle (17ns) 250 ma (20 -55ns) 225 ma standby (ttl) power supply current i cc 2 cs# v ih , v in v il , v in v ih 60ma full standby power supply current i cc 3 cs# v cc -0.2v v in vcc -0.2v or v in 0.2v ca 25 ma lpa 20 ma output low voltage v ol i ol = 6.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v note: dc test conditions: v il = 0.3v, v ih = vcc -0.3v
edi88512ca 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics C read cycle (v cc = 5.0v, vss = 0v, -55c t a +125c) parameter symbol 15ns 17ns 20ns 25ns 35ns 45ns 55ns units jedec alt. min max min max min max min max min max min max min max read cycle time t avav t rc 15 17 20 25 35 45 55 ns address access time t avqv t aa 15 17 20 25 35 45 55 ns chip enable access time t elqv t acs 15 17 20 25 35 45 55 ns chip enable to output in low z (1) t elqx t clz 2333333ns chip disable to output in high z (1) t ehqz t chz 070708010015020020ns output hold from address change t avqx t oh 0000000ns output enable to output valid t glqv t oe 8 8 10 12 15 25 30 ns output enable to output in low z (1) t glqx t olz 0000000ns output disable to output in high z(1) t ghqz t ohz 070708010015020020ns parameter symbol 15ns 17ns 20ns 25ns 35ns 45ns 55ns units jedec alt. min max min max min max min max min max min max min max write cycle time t avav t wc 15 17 20 25 35 45 55 ns chip enable to end of write t elwh t eleh t cw t cw 13 13 14 14 15 15 17 17 25 25 30 30 50 50 ns ns address setup time t avwl t avel t as t as 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns address valid to end of write t avwh t aveh t aw t aw 13 13 14 14 15 15 17 17 25 25 30 30 50 50 ns ns write pulse width t wlwh t wleh t wp t wp 13 13 14 14 15 15 17 17 25 25 30 30 45 45 ns ns write recovery time t whax t ehax t wr t wr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns data hold time t whdx t ehdx t dh t dh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns write to output in high z (1) t wlqz t whz 0 8 0 8 0 8 0 10 0 25 0 30 0 30 ns data to write time t dvwh t dveh t dw t dw 8 8 8 8 10 10 12 12 20 20 25 25 40 30 ns ns output active from end of write (1) t whqx t wlz 0000000 ns ac characteristics C write cycle (v cc = 5.0v, v ss = 0v, -55c t a +125c) 1. this parameter is guaranteed by design but not tested. 1. this parameter is guaranteed by design but not tested.
edi88512ca 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. write cycle 2, cs# controlled t aveh t eleh t ehax t wleh t dveh t ehdx t avav data valid high z data out t avel address data in we# cs# address data i/o read cycle 1 (we# high; oe#, cs# low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data out read cycle 2 (we# high) t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz oe# cs# fig. 2 timing waveform - read cycle fig. 4 write cycle - cs# controlled fig. 3 write cycle - we# controlled address data in write cycle 1, we# controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we# cs# data out
edi88512ca 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. characteristic low power version only sym conditions min typ max units data retention voltage data retention quiescent current v cc i ccdr v cc = 2.0v cs# v cc -0.2v 2 C C C C 2 v ma chip disable to data retention time operation recovery time t cdr t r v in v cc -0.2v or v in 0.2v 0 t avav C C C C ns ns data retention characteristics (edi88512lpa only) (-55c t a +125c) ws32k32-xhx fig. 5 data retention - cs# controlled data retention mode cs# = v cc -0.2v v cc cs# t cdr v cc 4.5v 4.5v t r data retention, cs# controlled
edi88512ca 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. package 9: 32 lead sidebrazed ceramic dip, smd 5962-95600xxmxa all dimensions are in inches pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 1.616 1.584 0.061 0.017 0.600 nom 0.060 0.040 0.620 0.600 package 326: 32 lead sidebrazed ceramic dip pin 1 indicator 0.020 0.016 0.200 0.125 0.100 typ 15 x 0.100 = 1.500 0.155 0.115 0.420 0.400 1.616 1.584 0.061 0.017 0.400 nom 1 1 package 140: 32 lead ceramic soj, smd 5962-95600xxmua 0.050 typ 0.444 0.430 0.840 0.820 0.155 0.106 0.379 0.010 0.006 0.019 0.015 all dimensions are in inches all dimensions are in inches
edi88512ca 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. +0.002 0.006 -0.001 0.838 max. 0.016 0.008 0.300 0.010 0.423 0.004 0.024 ref. 0.050 0.002 typ. 0.112 max. package 316: 36 pin ceramic flatpack, smd 5962-95600xxmta pin 1 0.019 0.015 0.040 0.030 0.395 0.385 0.125 0.100 0.050 typ 0.515 0.505 0.045 0.020 0.007 0.003 0.920 0.010 0.370 0.250 1.00 ref package 321: 32 pin thinpack? flatpack, smd 5962-95600xxmya package 344: 32 pin ceramic flatpack, smd 5962-95600xxm9a 0.050 typ 0.016 0.008 0.118 max. 0.020 0.030 0.008 0.005 0.427 0.429 0.838 max 0.567 0.559 all dimensions are in inches all dimensions are in inches all dimensions are in inches
edi88512ca 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. package 327: 36 lead ceramic soj, smd 5962-95600xxmma 0.050 typ 0.44 4 0.43 4 0.920 0.940 0.155 0.106 0.379 0.010 0.006 0.019 0.015 package 502: 36 lead ceramic lcc, smd 5962-95600xxmna (pending) 0.080 0.100 0.054 0.066 0.022 0.028 0.910 0.930 0.840 0.860 0.445 0.460 0.050 bsc 0.100 typ 0.115 0.135 0.009 typ 36 1 all dimensions are in inches all dimensions are in inches
edi88512ca 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 11 white electronic designs corp. reserves the right to change products or speci? cations without notice. edi 8 8 512 ca x x x ordering information white electronic designs sram organization, 512kx8 technology: ca = cmos standard power lpa = low power access time (ns) package type: c = 32 lead sidebrazed dip, 600 mil (package 9) k = 36 lead ceramic lcc (package 502) n = 32 lead ceramic soj (package 140) t = 32 lead sidebrazed dip, 400 mil (package 326) b32 = 32 pin ceramic thinpack? flatpack (package 321) f32 = 32 pin ceramic flatpack (package 344) f36 = 36 pin ceramic flatpack (package 316) n36 = 36 lead ceramic soj (package 327) device grade: b = mil-std-883 compliant m = military screened -55c t a +125c i = industrial -40c t a +85c c = commercial 0c t a +70c
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